Books & Videos

Inside the Machine

An Illustrated Introduction to Microprocessors and Computer Architecture

By Jon Stokes

Publisher: No Starch Press

Release Date: December 2010

Pages: 320

Read on Safari with a 10-day trial

Start your free trial now Buy on Amazon

Where’s the cart? Now you can get everything on Safari. To purchase books, visit Amazon or your favorite retailer. Questions? See our FAQ or contact customer service:

1-800-889-8969 / 707-827-7019
support@oreilly.com

Computers perform countless tasks ranging from the business critical to the recreational, but regardless of how differently they may look and behave, they're all amazingly similar in basic function. Once you understand how the microprocessor-or central processing unit (CPU)-works, you'll have a firm grasp of the fundamental concepts at the heart of all modern computing.

Inside the Machine, from the co-founder of the highly respected Ars Technica website, explains how microprocessors operate-what they do and how they do it. The book uses analogies, full-color diagrams, and clear language to convey the ideas that form the basis of modern computing. After discussing computers in the abstract, the book examines specific microprocessors from Intel, IBM, and Motorola, from the original models up through today's leading processors. It contains the most comprehensive and up-to-date information available (online or in print) on Intel's latest processors: the Pentium M, Core, and Core 2 Duo. Inside the Machine also explains technology terms and concepts that readers often hear but may not fully understand, such as "pipelining," "L1 cache," "main memory," "superscalar processing," and "out-of-order execution."

Includes discussion of:

Parts of the computer and microprocessor

Programming fundamentals (arithmetic instructions, memory accesses, control flow instructions, and data types)

Intermediate and advanced microprocessor concepts (branch prediction and speculative execution)

Intermediate and advanced computing concepts (instruction set architectures, RISC and CISC, the memory hierarchy, and encoding and decoding machine language instructions)

64-bit computing vs. 32-bit computing

Caching and performance

Inside the Machine is perfect for students of science and engineering, IT and business professionals, and the growing community of hardware tinkerers who like to dig into the guts of their machines.

Chapter 1 Basic Computing Concepts
1. The Calculator Model of Computing
2. The File-Clerk Model of Computing
3. The Register File
4. RAM: When Registers Alone Won't Cut It
5. A Closer Look at the Code Stream: The Program
6. A Closer Look at Memory Accesses: Register vs. Immediate
Chapter 2 The Mechanics of Program Execution
1. Opcodes and Machine Language
2. The Programming Model and the ISA
3. The Clock
4. Branch Instructions
5. Excursus: Booting Up
Chapter 3 Pipelined Execution
1. The Lifecycle of an Instruction
2. Basic Instruction Flow
3. Pipelining Explained
4. Applying the Analogy
Chapter 4 Superscalar Execution
1. Superscalar Computing and IPC
2. Expanding Superscalar Processing with Execution Units
3. Microarchitecture and the ISA
4. Challenges to Pipelining and Superscalar Design
Chapter 5 The Intel Pentium and Pentium Pro
1. The Original Pentium
2. The Intel P6 Microarchitecture: The Pentium Pro
3. Conclusion
Chapter 6 PowerPC Processors: 600 Series, 700 Series, and 7400
1. A Brief History of PowerPC
2. The PowerPC 601
3. The PowerPC 603 and 603e
4. The PowerPC 604
5. The PowerPC 604e
6. The PowerPC 750 (aka the G3)
7. The PowerPC 7400 (aka the G4)
8. Conclusion
Chapter 7 Intel's Pentium 4 vs. Motorola's G4e: Approaches and Design Philosophies
1. The Pentium 4's Speed Addiction
2. The General Approaches and Design Philosophies of the Pentium 4 and G4e
3. An Overview of the G4e's Architecture and Pipeline
4. Branch Prediction on the G4e and Pentium 4
5. An Overview of the Pentium 4's Architecture
6. An Overview of the Pentium 4's Pipeline
7. The Pentium 4's Instruction Window
Chapter 8 Intel's Pentium 4 vs. Motorola's G4e: The Back End
1. Some Remarks About Operand Formats
2. The Integer Execution Units
3. The Floating-Point Units (FPUs)
4. The Vector Execution Units
5. Conclusions
Chapter 9 64-Bit Computing and x86-64
1. Intel's IA-64 and AMD's x86-64
2. Why 64 Bits?
3. What Is 64-Bit Computing?
4. Current 64-Bit Applications
5. The 64-Bit Alternative: x86-64
6. Conclusion
Chapter 10 The G5: IBM's PowerPC 970
1. Overview: Design Philosophy
2. Caches and Front End
3. Branch Prediction
4. The Trade-Off: Decode, Cracking, and Group Formation
5. The PowerPC 970's Back End
6. Load-Store Units
7. Front-Side Bus
8. The Floating-Point Units
9. Vector Computing on the PowerPC 970
10. Floating-Point Issue Queues
11. The Performance Implications of the 970's Group Dispatch Scheme
12. Conclusions
Chapter 11 Understanding Caching and Performance
1. Caching Basics
2. Locality of Reference
3. Cache Organization: Blocks and Block Frames
4. Tag RAM
5. Fully Associative Mapping
6. Direct Mapping
7. N-Way Set Associative Mapping
8. Temporal and Spatial Locality Revisited: Replacement/Eviction Policies and Block Sizes
9. Write Policies: Write-Through vs. Write-Back
10. Conclusions
Chapter 12 Intel's Pentium M, Core Duo, and Core 2 Duo
1. Code Names and Brand Names
2. The Rise of Power-Efficient Computing
3. Power Density
4. The Pentium M
5. Core Duo/Solo
6. Core 2 Duo
7. Core's Back End

Appendix Bibliography and Suggested Reading
1. Online Resources
Colophon
Appendix Updates

Books & Videos

Inside the Machine

An Illustrated Introduction to Microprocessors and Computer Architecture

Read on Safari with a 10-day trial

Table of Contents

Chapter 1 Basic Computing Concepts

The Calculator Model of Computing

The File-Clerk Model of Computing

The Register File

RAM: When Registers Alone Won't Cut It

A Closer Look at the Code Stream: The Program

A Closer Look at Memory Accesses: Register vs. Immediate

Chapter 2 The Mechanics of Program Execution

Opcodes and Machine Language

The Programming Model and the ISA

The Clock

Branch Instructions

Excursus: Booting Up

Chapter 3 Pipelined Execution

The Lifecycle of an Instruction

Basic Instruction Flow

Pipelining Explained

Applying the Analogy

Chapter 4 Superscalar Execution

Superscalar Computing and IPC

Expanding Superscalar Processing with Execution Units

Microarchitecture and the ISA

Challenges to Pipelining and Superscalar Design

Chapter 5 The Intel Pentium and Pentium Pro

The Original Pentium

The Intel P6 Microarchitecture: The Pentium Pro

Conclusion

Chapter 6 PowerPC Processors: 600 Series, 700 Series, and 7400

A Brief History of PowerPC

The PowerPC 601

The PowerPC 603 and 603e

The PowerPC 604

The PowerPC 604e

The PowerPC 750 (aka the G3)

The PowerPC 7400 (aka the G4)

Conclusion

Chapter 7 Intel's Pentium 4 vs. Motorola's G4e: Approaches and Design Philosophies

The Pentium 4's Speed Addiction

The General Approaches and Design Philosophies of the Pentium 4 and G4e

An Overview of the G4e's Architecture and Pipeline

Branch Prediction on the G4e and Pentium 4

An Overview of the Pentium 4's Architecture

An Overview of the Pentium 4's Pipeline

The Pentium 4's Instruction Window

Chapter 8 Intel's Pentium 4 vs. Motorola's G4e: The Back End

Some Remarks About Operand Formats

The Integer Execution Units

The Floating-Point Units (FPUs)

The Vector Execution Units

Conclusions

Chapter 9 64-Bit Computing and x86-64

Intel's IA-64 and AMD's x86-64

Why 64 Bits?

What Is 64-Bit Computing?

Current 64-Bit Applications

The 64-Bit Alternative: x86-64

Conclusion

Chapter 10 The G5: IBM's PowerPC 970

Overview: Design Philosophy

Caches and Front End

Branch Prediction

The Trade-Off: Decode, Cracking, and Group Formation

The PowerPC 970's Back End

Load-Store Units

Front-Side Bus

The Floating-Point Units

Vector Computing on the PowerPC 970

Floating-Point Issue Queues

The Performance Implications of the 970's Group Dispatch Scheme

Conclusions

Chapter 11 Understanding Caching and Performance

Caching Basics

Locality of Reference

Cache Organization: Blocks and Block Frames

Tag RAM