Books & Videos

Table of Contents

  1. Chapter 1 Basic Computing Concepts

    1. The Calculator Model of Computing

    2. The File-Clerk Model of Computing

    3. The Register File

    4. RAM: When Registers Alone Won't Cut It

    5. A Closer Look at the Code Stream: The Program

    6. A Closer Look at Memory Accesses: Register vs. Immediate

  2. Chapter 2 The Mechanics of Program Execution

    1. Opcodes and Machine Language

    2. The Programming Model and the ISA

    3. The Clock

    4. Branch Instructions

    5. Excursus: Booting Up

  3. Chapter 3 Pipelined Execution

    1. The Lifecycle of an Instruction

    2. Basic Instruction Flow

    3. Pipelining Explained

    4. Applying the Analogy

  4. Chapter 4 Superscalar Execution

    1. Superscalar Computing and IPC

    2. Expanding Superscalar Processing with Execution Units

    3. Microarchitecture and the ISA

    4. Challenges to Pipelining and Superscalar Design

  5. Chapter 5 The Intel Pentium and Pentium Pro

    1. The Original Pentium

    2. The Intel P6 Microarchitecture: The Pentium Pro

    3. Conclusion

  6. Chapter 6 PowerPC Processors: 600 Series, 700 Series, and 7400

    1. A Brief History of PowerPC

    2. The PowerPC 601

    3. The PowerPC 603 and 603e

    4. The PowerPC 604

    5. The PowerPC 604e

    6. The PowerPC 750 (aka the G3)

    7. The PowerPC 7400 (aka the G4)

    8. Conclusion

  7. Chapter 7 Intel's Pentium 4 vs. Motorola's G4e: Approaches and Design Philosophies

    1. The Pentium 4's Speed Addiction

    2. The General Approaches and Design Philosophies of the Pentium 4 and G4e

    3. An Overview of the G4e's Architecture and Pipeline

    4. Branch Prediction on the G4e and Pentium 4

    5. An Overview of the Pentium 4's Architecture

    6. An Overview of the Pentium 4's Pipeline

    7. The Pentium 4's Instruction Window

  8. Chapter 8 Intel's Pentium 4 vs. Motorola's G4e: The Back End

    1. Some Remarks About Operand Formats

    2. The Integer Execution Units

    3. The Floating-Point Units (FPUs)

    4. The Vector Execution Units

    5. Conclusions

  9. Chapter 9 64-Bit Computing and x86-64

    1. Intel's IA-64 and AMD's x86-64

    2. Why 64 Bits?

    3. What Is 64-Bit Computing?

    4. Current 64-Bit Applications

    5. The 64-Bit Alternative: x86-64

    6. Conclusion

  10. Chapter 10 The G5: IBM's PowerPC 970

    1. Overview: Design Philosophy

    2. Caches and Front End

    3. Branch Prediction

    4. The Trade-Off: Decode, Cracking, and Group Formation

    5. The PowerPC 970's Back End

    6. Load-Store Units

    7. Front-Side Bus

    8. The Floating-Point Units

    9. Vector Computing on the PowerPC 970

    10. Floating-Point Issue Queues

    11. The Performance Implications of the 970's Group Dispatch Scheme

    12. Conclusions

  11. Chapter 11 Understanding Caching and Performance

    1. Caching Basics

    2. Locality of Reference

    3. Cache Organization: Blocks and Block Frames

    4. Tag RAM

    5. Fully Associative Mapping

    6. Direct Mapping

    7. N-Way Set Associative Mapping

    8. Temporal and Spatial Locality Revisited: Replacement/Eviction Policies and Block Sizes

    9. Write Policies: Write-Through vs. Write-Back

    10. Conclusions

  12. Chapter 12 Intel's Pentium M, Core Duo, and Core 2 Duo

    1. Code Names and Brand Names

    2. The Rise of Power-Efficient Computing

    3. Power Density

    4. The Pentium M

    5. Core Duo/Solo

    6. Core 2 Duo

    7. Core's Back End

  1. Appendix Bibliography and Suggested Reading

    1. Online Resources

  2. Colophon

  3. Appendix Updates